GTCAD Publication, Topical List EDA with Machine Learning
  1. Anthony Agnesina, Etienne Lepercq, Jose Escobedo, and Sung Kyu Lim, "Improving FPGA-based Logic Emulation Systems through Machine Learning," ACM Transactions on Design Automation of Electronic Systems. Vol. 25, No. 5, pp. 1-20, 2020. (pdf)
  2. Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim, "A Clock Tree Prediction and Optimization Framework using Generative Adversarial Learning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 41, No. 9, pp. 3104-3117, 2022. (pdf)
  3. Yi-Chen Lu, Sai Pentapati, Lingjun Zhu, Gauthaman Murali, Kambiz Samadi, and Sung Kyu Lim, "A Machine Learning Powered Tier Partitioning Methodology for Monolithic 3D ICs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 41, No. 11, pp. 4575-4586, 2022. (pdf)
  4. Anthony Agnesina, Kyungwook Chang, and Sung Kyu Lim, "Parameter Optimization of VLSI Placement through Deep Reinforcement Learning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 42, No. 4, pp. 1295-1308, 2022. (pdf)
  5. Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, and Sung Kyu Lim, "ECO-GNN: Signoff Power Prediction using Graph Neural Networks with Subgraph Approximation," ACM Transactions on Design Automation of Electronic Systems. Vol. 28, No. 4, pp. 1-22, 2023. (pdf)
  6. Anthony Agnesina, Yi-Chen Lu, and Sung Kyu Lim, "Circuit Optimization for 2D and 3D ICs with Machine Learning," in Machine Learning Applications in Electronic Design Automation, edited by Haoxing Ren and Jiang Hu, Springer, 2023. (ISBN 978-3-031-13073-1).
  7. Gauthaman Murali, Anthony Agnesina, and Sung Kyu Lim, "A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers," ACM Transactions on Design Automation of Electronic Systems. (pdf)
  8. Pruek Vanna-iampikul, Yi-Chen Lu, Da Eun Shim, and Sung Kyu Lim, "GNN-Based Multi-Bit Flip-Flop Clustering and Post-Clustering Design Optimization for Energy-Efficient 3D ICs," ACM Transactions on Design Automation of Electronic Systems. (pdf)
  9. Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim, "GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning", ACM Transactions on Design Automation of Electronic Systems. Vol. 29, No. 2, pp. 1-17, 2024. (pdf)
  10. Gauthaman Murali, Min Gyu Park, Sung Kyu Lim, "3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators," IEEE Transactions on Very Large Scale Integration Systems, Accepted for publication.
  11. Anthony Agnesina, Etienne Lepercq, Jose Escobedo, and Sung Kyu Lim, "Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning," IEEE International Conference on Computer-Aided Design, 2019. Nominated for Best Paper Award. (pdf)
  12. Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim, "GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization," IEEE International Conference on Computer-Aided Design, 2019. Nominated for Best Paper Award. (pdf)
  13. Yi-Chen Lu, Sai Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim, "TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs," ACM Design Automation Conference, 2020. Nominated for Best Paper Award. (pdf)
  14. Anthony Agnesina, Kyungwook Chang, and Sung Kyu Lim, "VLSI Placement Parameter Optimization using Deep Reinforcement Learning," IEEE International Conference on Computer-Aided Design, 2020. (pdf)
  15. Yi-Chen Lu, Siddhartha Nath, Sai Pentapati and Sung Kyu Lim, "A Fast Learning-Driven Signoff Power Optimization Framework," IEEE International Conference on Computer-Aided Design, 2020. (pdf)
  16. Anthony Agnesina, Sai Pentapati, and Sung Kyu Lim, "A General Framework For VLSI Tool Parameter Optimization with Deep Reinforcement Learning," Workshop on ML for Systems at NeurIPS, 2021. (pdf)
  17. Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim, "VLSI Placement Optimization using Graph Neural Networks," Workshop on ML for Systems at NeurIPS, 2021. (pdf)
  18. Sai Pentapati, Bon Woong Ku, and Sung Kyu Lim, "ML-based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization," ACM International Symposium on Physical Design, 2021. (pdf)
  19. Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim, "The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks," ACM International Symposium on Physical Design, 2021. Nominated for Best Paper Award. (pdf)
  20. Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim, "RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning", ACM Design Automation Conference, 2021. (pdf)
  21. Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim, "Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning", IEEE International Conference on Computer-Aided Design, 2021. (pdf)
  22. Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, and Sung Kyu Lim, "ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs", ACM International Symposium on Physical Design, 2022.
  23. Yi-Chen Lu and Sung Kyu Lim, "On Advancing Physical Design using Graph Neural Networks", IEEE International Conference on Computer-Aided Design, 2022. Invited Paper. (pdf)
  24. Yi-Chen Lu, Wei-Ting Chan, Vishal Khandelwal, and Sung Kyu Lim, "Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction", ACM/IEEE Workshop on Machine Learning for CAD, 2022. (pdf)
  25. Yi-Chen Lu, Tian Yang, Sung Kyu Lim, and Haoxing Ren, "Placement Optimization via PPA-Directed Graph Clustering", ACM/IEEE Workshop on Machine Learning for CAD, 2022. Best Student Paper Award. (pdf)
  26. Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim, "DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning", ACM International Symposium on Physical Design, 2023. (pdf)
  27. Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, and Sung Kyu Lim, "RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning", ACM Design Automation Conference, 2023. Best Paper Award. (pdf)
  28. Hao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, and Sung Kyu Lim, "FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning", ACM International Symposium on Physical Design, 2024.
  29. Hao-Hsiang Hsiao, Pruek Vanna-iampikul, Yi-Chen Lu, and Sung Kyu Lim, "ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization", ACM Design Automation Conference, 2024. (pdf)
  30. Nesara Eranna Bethur, Pruek Vanna-iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto Garcia-Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, and Sung Kyu Lim, "GNN-assisted Back-side Clock Routing Methodology for Advance Technologies", ACM Design Automation Conference, 2024. (pdf)
  31. Zheng Yang, Zhen Zhuang, Bei Yu, Tsung-Yi Ho, Martin D.F. Wong, and Sung Kyu Lim, "ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs", ACM International Symposium on Physical Design, 2025.
2.5D ICs and Chiplet/Interposer Co-design
  1. Sung Kyu Lim, "Physical Design for 3D System-On-Package: Challenges and Opportunities," IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 532-539, 2005. (pdf)
  2. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Multi-objective Module Placement For 3D System-On-Package," IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 5, pp. 553-557, 2006. (pdf)
  3. Jacob Minz, Eric Wong, Mohit Pathak, and Sung Kyu Lim, "Placement and Routing for 3D System-On-Package Designs," IEEE Transactions on Components and Packaging Technologies, Vol. 29, No. 3, pp. 644-657, 2006. (pdf)
  4. Jacob Minz and Sung Kyu Lim, "Block-level 3D Global Routing With an Application to 3D Packaging," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 2248-2257, 2006. (pdf)
  5. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 4, pp. 805-812, 2007. (pdf)
  6. Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Mechanical Stress Impact on 3D IC Reliability and Mobility Variations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1694-1707, 2013. (pdf)
  7. Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, and Sung Kyu Lim, "Architecture, Chip, and Package Co-design Flow for Interposer-based 2.5D Chiplet Integration Enabling Heterogeneous IP Reuse," IEEE Transactions on Very Large Scale Integration Systems. Vol. 28, No. 11, pp. 2424-2437, 2020. (pdf)
  8. Minah Lee, Arvind Singh, Hakki M.Torun, Jinwoo Kim, Sung Kyu Lim, Madhavan Swaminathan, and Saibal Mukhopadhyay, "Automated I/O Library Generation for Interposer-based System-in-Package Integration of Multiple Heterogeneous Dies," IEEE Transactions on Components, Packaging, and Manufacturing Technology. Vol. 10, No. 1, pp. 111-122, 2020. (pdf)
  9. Heechun Park, Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Majid Ahadi Dolatsara, Mohammed Nabeel, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay, Johann Knechtel, and Sung Kyu Lim, "Design Flow for Active Interposer-Based 2.5D ICs and Study of RISC-V Architecture with Secure NoC", IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10, No. 12, pp. 2047-2060, 2020. (pdf)
  10. Majid Ahadi Dolatsara, Jose Hejase, Wiren Dale Becker, Jinwoo Kim, Sung Kyu Lim, and Madhavan Swaminathan, "Worst-case Eye Analysis of High-speed Channels Based on Bayesian Optimization," IEEE Transactions on Electromagnetic Compatibility. Vol. 63, No. 1, pp. 246-258, 2021. Richard B. Shultz Best Paper Award. (pdf).
  11. Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna and Sung Kyu Lim, "Clock Delivery Network Design and Analysis for Interposer-based 2.5D Heterogeneous Systems", IEEE Transactions on Very Large Scale Integration Systems. Vol. 29, No. 1, pp. 605-616, 2021. (pdf)
  12. Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, and Sung Kyu Lim, "Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology. Vol. 11, No. 12, pp. 2148-2157, 2021. (pdf)
  13. Pruek Vanna-Iampikul, Seungmin Woo, Serhat Erdogan, Lingjun Zhu, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, Madhavan Swaminathan and Sung Kyu Lim, "Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Accepted for publication.
  14. Jacob Minz and Sung Kyu Lim, "Layer Assignment for System on Packages," ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 31-37, 2004. (pdf)
  15. Jacob Minz, Mohit Pathak, and Sung Kyu Lim, "Net and Pin Distribution for 3D Package Global Routing," Design, Automation and Test in Europe, pp. 1410-1411, 2004. (pdf)
  16. Ramprasad Ravichandran, Jacob Minz, Mohit Pathak, Siddharth Easwar, and Sung Kyu Lim, "Physical Layout Automation for System-On-Packages," IEEE Electronic Components and Technology Conference, pp. 41-48, 2004. (pdf)
  17. Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, and Sung Kyu Lim, "Multi-layer Floorplanning for Reliable System-on-Package," IEEE International Symposium on Circuits and Systems, pp. 69-72, 2004. (pdf)
  18. Jacob Minz and Sung Kyu Lim, "A Global Router for System-on-Package Targeting Layer and Crosstalk Minimization," IEEE Electrical Performance of Electronic Packaging, pp. 99-102, 2004. (pdf)
  19. Jacob Minz, Eric Wong, and Sung Kyu Lim, "Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package," IEEE Electronic Components and Technology Conference, pp. 824-831, 2005. (pdf)
  20. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Power Noise-aware 3D Floorplanning for System-On-Package," IEEE Electrical Performance of Electronic Packaging, pp. 259-262, 2005. (pdf)
  21. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," Design, Automation and Test in Europe, pp. 337-338, 2006. (pdf)
  22. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Effective Thermal Via and Decoupling Capacitor Insertion Targeting 3D System-On-Package," IEEE Electronic Components and Technology Conference, pp. 1795-1801, 2006. (pdf)
  23. Moongon Jung and Sung Kyu Lim, "Chip/Package Co-analysis of Mechanical Reliability in TSV-based 3D ICs," IEEE Workshop on Chip-Packaging Co-Design for High Performance Electronic Systems, 2011.
  24. Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs," ACM Design Automation Conference, 2012. Nominated for Best Paper Award. (pdf)
  25. Gokul Kumar, Tapobrata Bandyopadhyay, Venky Sundaram, Sung Kyu Lim, and Rao Tummala, "Ultra-high I/O Density Glass/Silicon Interposers for High Bandwidth Smart Mobile Applications," IEEE Electronic Components and Technology Conference, 2011. (pdf)
  26. Taigon Song and Sung Kyu Lim, "Co-design and Co-simulation of 3D IC and Silicon Interposer Power Distribution Network," IEEE Workshop on Chip-Packaging Co-Design for High Performance Electronic Systems, 2011.
  27. Taigon Song and Sung Kyu Lim, "A Fine-Grained Co-Simulation Methodology for IR-drop Noise in Silicon Interposer and TSV-based 3D IC," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 239-242, 2011. (pdf)
  28. Taigon Song, Noah Sturcken, Krit Athikulwongse, Kenneth Shepard, and Sung Kyu Lim, "Thermal Analysis and Optimization of 2.5-D Integrated Voltage Regulator," IEEE Electrical Performance of Electronic Packaging and Systems, 2012. (pdf)
  29. Darryl Kostka, Taigon Song, and Sung Kyu Lim, "3D IC-Package-Board Co-analysis Using 3D EM Simulation for Mobile Applications," IEEE Electronic Components and Technology Conference, 2013. (pdf)
  30. Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging," IEEE Conference on Electrical Performance of Electronic Packaging and Systems, 2017. (pdf)
  31. Yarui Peng, Dusan Petranovic, and Sung Kyu Lim, "Die-to-Package Coupling Extraction for Fan-Out Wafer-Level-Packaging", IEEE Electrical Design of Advanced Packaging and Systems Symposium, 2017. Best Paper Award. (pdf)
  32. M. Lee, J. Kim, A. Singh, H. M. Torun, M. Swaminathan, S. K. Lim, and S. Mukhopadhyay, "On the Design of Energy-Efficient I/O Circuits for Interposer-based 2.5D System-in-Package," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2018. (pdf)
  33. Minah Lee, Arvind Singh, Hakki Mert Torun, Jinwoo Kim, Sung Kyu Lim, Madhavan Swaminathan, and Saibal Mukhopadhyay, "Automated Generation of All-Digital IO Library Cells for System-in-Package Integration of Multiple Dies," IEEE Electrical Performance of Electronic Packaging and Systems, 2018. (pdf)
  34. Minah Lee, Arvind Singh, Hakki Mert Torun, Jinwoo Kim, Sung Kyu Lim, Madhavan Swaminathan, and Saibal Mukhopadhyay, "Automated Generation of All-Digital I/O Library Cells for Multiple Dies in System-in-Package Integration," Government Microcircuit Application and Critical Technology Conference (GOMACTech), 2019.
  35. Jinwoo Kim, Eric Qin, Heechun Park, Tushar Krishna, and Sung Kyu Lim, "Enabling Heterogeneous IP Reuse with Interposer-based 2.5D ICs and Custom Interface Protocol," Government Microcircuit Application and Critical Technology Conference (GOMACTech), 2019.
  36. Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna and Sung Kyu Lim, "Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse," ACM Design Automation Conference, 2019. (pdf)
  37. Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Torun, Madhavan Swaminathan, Saibal Mukhopadhyay and Sung Kyu Lim, "Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration," IEEE International Conference on Computer Design, 2020. Best Paper Award. (pdf)
  38. Pruek Vanna-iampikul, Lingjun Zhu, Serhat Erdogan, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, and Sung Kyu Lim, "Glass Interposer Integration of Logic and Memory Chiplets: PPA and Signal/Power Integrity Benefits", ACM Design Automation Conference, 2023. (pdf)
  39. Jonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, and Krishnendu Chakrabarty, "Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation", Design, Automation and Test in Europe, 2023. (pdf)
  40. Seungmin Woo, Pruek Vanna-iampikul, and Sung Kyu Lim, "AI-Driven Evaluation and Optimization of Bump Pitch Effects on Chiplet and Interposer Design Quality", IEEE/ACM International Conference on Computer-Aided Design, 2024. (pdf)
3D IC Test Chip Development
  1. Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)," IEEE Transactions on Computers, Vol. 64, No. 1, pp. 112-125, 2015. (pdf)
  2. Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory," IEEE Custom Integrated Circuits Conference, 2010. Intel/CICC Student Scholarship Award. (pdf)
  3. Dean Lewis, Michael Healy, Mohammad Hossain, Tzu-Wei Lin, Mohit Pathak, Hemant Sane, Sung Kyu Lim, Gabriel H. Loh, and Hsien-Hsin S. Lee, "Design and Test of 3D-MAPS, a 3D Die-Stack Many-Core Processor," IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010. (pdf)
  4. Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim, "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory," IEEE International Solid-State Circuits Conference, 2012. (pdf)
Buffering and Signal Integrity for 3D ICs
  1. Young-Joon Lee, Mohit Pathak, Chang Liu, Moongon Jung, and Sung Kyu Lim, "Design and Timing Optimization of a 3D Stacked Microprocessor," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2010.
  2. Young-Joon Lee and Sung Kyu Lim, "Timing Analysis and Optimization for 3D Stacked Multi-Core Microprocessors," IEEE International 3D System Integration Conference, 2010. (pdf)
  3. Young-Joon Lee and Sung Kyu Lim, "Fast Delay Estimation with Buffer Insertion for Through-Silicon-Via-Based 3D Interconnects," IEEE International Symposium on Quality Electronic Design, 2012. (pdf)
  4. Young-Joon Lee, Inki Hong, and Sung Kyu Lim, "Slew-Aware Buffer Insertion for Through-Silicon-Via-Based 3D ICs," IEEE Custom Integrated Circuits Conference, 2012. Invited Paper. (pdf)
Clock Routing for 3D ICs
  1. Xin Zhao, Jacob Minz, and Sung Kyu Lim, "Low-Power and Reliable Clock Network Design for Through Silicon Via based 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 2, pp. 247-259, 2011. (pdf)
  2. Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Low-Power Clock Tree Design for Pre-Bond Testing of 3D Stacked ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 5, pp. 732-745, 2011. (pdf)
  3. Kwanyeob Chae, Xin Zhao, Sung Kyu Lim, and Saibal Mukhopadhyay, "Tier-Adaptive-Body-Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 3, No. 10, pp. 1720-1730, 2013. (pdf)
  4. Sai Manoj, Hao Yu, Yang Shang, Chuan Seng Tan, and Sung Kyu Lim, "Reliable 3D Clock-tree Synthesis Considering Nonlinear Capacitive TSV Model with Electrical-thermal-mechanical Coupling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1734-1747, 2013. (pdf)
  5. Jacob Minz, Xin Zhao, and Sung Kyu Lim, "Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 504-509, 2008. (pdf)
  6. Xin Zhao, Dean Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs," IEEE International Conference on Computer-Aided Design, 2009. Nominated for Best Paper Award. (pdf)
  7. Krit Athikulwongse, Xin Zhao, and Sung Kyu Lim, "Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets," IEEE/ACM Asia South Pacific Design Automation Conference, 2010. (pdf)
  8. Xin Zhao and Sung Kyu Lim, "Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs," IEEE/ACM Asia South Pacific Design Automation Conference, 2010. (pdf)
  9. Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, and David Z. Pan, "Robust Clock Tree Synthesis with Timing Yield Optimization for 3D ICs," IEEE/ACM Asia South Pacific Design Automation Conference, 2011. (pdf)
  10. Xin Zhao, Saibal Mukhopadhyay, and Sung Kyu Lim, "Variation-Tolerant and Low-Power Clock Network Design for 3D ICs," IEEE Electronic Components and Technology Conference, 2011. (pdf)
  11. Xin Zhao and Sung Kyu Lim, "Through-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs," IEEE/ACM Asia South Pacific Design Automation Conference, 2012. (pdf)
  12. Xin Zhao and Sung Kyu Lim, "TSV Array Utilization in Low-Power 3D Clock Network Design," IEEE International Symposium on Low Power Electronics and Design, 2012. Nominated for Best Paper Award. (pdf)
  13. Yang Shang, Chun Zhang, Hao Yu, Xin Zhao, and Sung Kyu Lim, "Thermal-reliable 3D Clock-tree Synthesis Considering Nonlinear Electrical-thermal-coupled TSV Model," IEEE/ACM Asia South Pacific Design Automation Conference, 2013. (pdf)
  14. Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, and Qiang Xu, "On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement," IEEE International Test Conference, 2015. (pdf)
Cooling 3D ICs with Microfluidic Channels
  1. Yoon Jo Kim, Yogendra K. Joshi, Andrei G. Fedorov, Young-Joon Lee, and Sung Kyu Lim, "Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional IC with Non-Uniform Heat Flux," ASME Journal of Heat Transfer, Vol. 132(4), 2010. (pdf)
  2. Young-Joon Lee and Sung Kyu Lim, "Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 11, pp. 1635-1648, 2011. (pdf)
  3. Young-Joon Lee and Sung Kyu Lim, "Co-Optimization of Signal, Power, and Thermal Distribution Networks for 3D ICs," IEEE Symposium on Electrical Design of Advanced Packaging and Systems, pp. 163-166, 2008. (pdf)
  4. Young-Joon Lee, Yoon-Jo Kim, Gang Huang, Muhannad Bakir, Yogendra Joshi, Andrei Fedorov, and Sung Kyu Lim, "Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs," Design, Automation and Test in Europe, pp. 610-615, 2009. (pdf)
  5. Young-Joon Lee and Sung Kyu Lim, "Routing Optimization of Multi-modal Interconnects In 3D ICs," IEEE Electronic Components and Technology Conference, pp. 32-39, 2009. (pdf)
  6. Young-Joon Lee, Mike Healy, and Sung Kyu Lim, "Co-design of Reliable Signal and Power Interconnects in 3D Stacked ICs," IEEE International Interconnect Technology Conference, pp. 56-58, 2009. (pdf)
  7. Yoon Jo Kim, Yogendra K. Joshi, Andrei G. Fedorov, Young-Joon Lee, and Sung Kyu Lim, "Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional IC with Non-Uniform Heat Flux," ASME Conference on Nanochannels, Microchannels and Minichannels, 2009.
  8. Young-Joon Lee, Rohan Goel, and Sung Kyu Lim, "Multi-functional Interconnect Co-optimization for Fast and Reliable 3D Stacked ICs," IEEE International Conference on Computer-Aided Design, 2009. (pdf)
Design-for-Testing for 3D ICs
  1. Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay, "Pre-bond and Post-bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 11, pp. 1718-1727, 2011. (pdf)
  2. Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, and Sung Kyu Lim, "Scan Test of Die Logic in 3D ICs Using TSV Probing," IEEE Transactions on Very Large Scale Integration Systems, Vol. 23, No. 2, pp. 317-330, 2015. (pdf)
  3. Shreepad Panth and Sung Kyu Lim, "Probe-Pad Placement for Prebond Test of 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 6, No. 4, pp. 637-644, 2016. (pdf)
  4. Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay, "Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System," IEEE International Conference on Computer-Aided Design, 2010. (pdf)
  5. Shreepad Panth and Sung Kyu Lim, "Scan Chain and Power Delivery Network Synthesis for Pre-Bond Test of 3D ICs," IEEE VLSI Test Symposium, 2011. (pdf)
  6. Dean Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, and Hsien-Hsin Lee, "Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores," IEEE International Conference on Computer Design, pp. 90-95, 2011. (pdf)
  7. Shreepad Panth and Sung Kyu Lim, "Transition Delay Fault Testing of 3D ICs with IR-Drop Study," IEEE VLSI Test Symposium, pp. 270-275, 2012. (pdf)
  8. Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, and Sung Kyu Lim, "Scan Test of Die Logic in 3D ICs Using TSV Probing," IEEE International Test Conference, 2012. (pdf)
  9. Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, and Sung Kyu Lim, "TSV Stress-Aware ATPG for 3D Stacked ICs," IEEE Asian Test Symposium, 2012. Best Paper Award. (pdf)
  10. Sergej Deutsch, Krishnendu Chakrabarty, Shreepad Panth, and Sung Kyu Lim, "TSV Stress-Aware ATPG for 3D Stacked ICs," IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2012.
  11. Shreepad Panth, Kambiz Samadi, and Sung Kyu Lim, "Test-TSV Estimation During 3D-IC Partitioning," IEEE International 3D Systems Integration Conference, 2013. (pdf)
Electromigration in 3D ICs
  1. Xin Zhao, Michael Scheuermann, and Sung Kyu Lim, "Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 4, No. 1, pp. 123-133, 2014. (pdf)
  2. Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 12, pp. 1873 - 1885, 2014. (pdf)
  3. Jiwoo Pak, Mohit Pathak, Sung Kyu Lim and David Z. Pan, "Modeling of Electromigration in Through-Silicon-Via Based 3D IC," IEEE Electronic Components and Technology Conference, 2011. (pdf)
  4. Mohit Pathak, Jiwoo Pak, David Z. Pan and Sung Kyu Lim, "Electromigration Modeling and Full-chip Reliability Analysis for BEOL Interconnect in TSV-based 3D ICs," IEEE International Conference on Computer-Aided Design, 2011. (pdf)
  5. Xin Zhao, Michael Scheuermann, and Sung Kyu Lim, "Analysis of DC Current Crowding in Through-Silicon-Vias and Its Impact on Power Integrity in 3D ICs," ACM Design Automation Conference, 2012. (pdf)
  6. Jiwoo Pak, Sung Kyu Lim, and David Z. Pan, "Electromigration-aware Routing for 3D ICs with Stress-aware EM Modeling," IEEE International Conference on Computer-Aided Design, 2012. (pdf)
  7. Xin Zhao, Yang Wan, Michael Scheuermann and Sung Kyu Lim, "Transient Modeling of TSV-Wire Electromigration and Lifetime Analysis of Power Distribution Network for 3D ICs," IEEE International Conference on Computer-Aided Design, 2013. (pdf)
  8. Jiwoo Pak, Sung Kyu Lim and David Z. Pan, "Electromigration Study for Multi-scale Power/Ground Vias in TSV-based 3D ICs," IEEE International Conference on Computer-Aided Design, 2013. (pdf)
Floorplanning and Placement for 3D ICs
  1. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Multi-objective Module Placement For 3D System-On-Package," IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 5, pp. 553-557, 2006. (pdf)
  2. Jacob Minz, Eric Wong, Mohit Pathak, and Sung Kyu Lim, "Placement and Routing for 3D System-On-Package Designs," IEEE Transactions on Components and Packaging Technologies, Vol. 29, No. 3, pp. 644-657, 2006. (pdf)
  3. Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh, "Multi-Objective Microarchitectural Floorplanning For 2D And 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Ciruits and Systems, Vol. 26, No. 1, pp. 38-52, 2007. (pdf)
  4. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 11, pp. 2023-2034, 2007. (pdf)
  5. Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout," IEEE Transactions on Very Large Scale Integration Systems, Vol. 21, No. 5, pp. 862-874, 2013. (pdf)
  6. Krit Athikulwongse, Mongkol Ekpanyapong, and Sung Kyu Lim, "Exploiting Die-to-Die Thermal Coupling in 3D IC Placement," IEEE Transactions on Very Large Scale Integration Systems, Vol. 22, No. 10, pp. 2145-2155, 2014. (pdf)
  7. Sung Kyu Lim, "Research Needs for TSV-Based 3D IC Architectural Floorplanning," Journal of Information and Communication Convergence Engineering, Vol. 12, No. 1, pp. 46-52, 2014. (pdf)
  8. Eric Wong and Sung Kyu Lim, "3D Floorplanning with Thermal Vias," Design, Automation and Test in Europe, pp. 878-883, 2006. (pdf)
  9. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Effective Thermal Via and Decoupling Capacitor Insertion Targeting 3D System-On-Package," IEEE Electronic Components and Technology Conference, pp. 1795-1801, 2006. (pdf)
  10. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," IEEE International Conference on Computer-Aided Design, pp. 395-400, 2006. (pdf)
  11. Eric Wong and Sung Kyu Lim, "Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs," IEEE International Conference on Computer Design, pp. 267-272, 2007. (pdf)
  12. Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout," IEEE International Conference on Computer-Aided Design, 2009. (pdf)
  13. Mohit Pathak, Young-Joon Lee, Thomas Moon, and Sung Kyu Lim, "Through Silicon Via Management during 3D Physical Design: When to Add and How Many?," IEEE International Conference on Computer-Aided Design, 2010. (pdf)
  14. Dae Hyun Kim, Rasit Topaloglu, and Sung Kyu Lim, "TSV Density-driven Global Placement for 3D Stacked ICs," International SoC Design Conference, pp. 135-138, 2011. (pdf)
  15. Dae Hyun Kim, Rasit Topaloglu, and Sung Kyu Lim, "Block-level 3D IC Design with Through-Silicon-Via Planning," IEEE/ACM Asia South Pacific Design Automation Conference, 2012. (pdf)
  16. Krit Athikulwongse, Mohit Pathak, and Sung Kyu Lim, "Exploiting Die-to-Die Thermal Coupling in 3D IC Placement," ACM Design Automation Conference, 2012. (pdf)
  17. Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim, "Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs," IEEE/ACM Asia South Pacific Design Automation Conference, 2013. (pdf)
Future 3D IC Design Study
  1. Dae Hyun Kim and Sung Kyu Lim, "Design Quality Trade-off Studies for 3D ICs Built with Sub-micron TSVs and Future Devices," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 2, pp. 240-248, 2012. (pdf)
  2. Michael Healy and Sung Kyu Lim, "A Study of Stacking Limit and Scaling in 3D ICs: an Interconnect Perspective," IEEE Electronic Components and Technology Conference, pp. 1213-1220, 2009. (pdf)
  3. Dae Hyun Kim and Sung Kyu Lim, "Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs," IEEE International Interconnect Technology Conference, 2011. (pdf)
  4. Dae Hyun Kim, Suyoun Kim, and Sung Kyu Lim, "Impact of Sub-micron Through-Silicon Vias on the Quality of Today and Future 3D IC Designs," ACM/IEEE International Workshop on System Level Interconnect Prediction, 2011. (pdf)
  5. Kaiyuan Yang, Dae Hyun Kim, and Sung Kyu Lim, "Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices," IEEE International Symposium on Quality Electronic Design, 2012. (pdf)
Interconnect Prediction for 3D ICs
  1. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3D Stacked ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 9, pp. 1384-1395, 2014. (pdf)
  2. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs," IEEE International Interconnect Technology Conference, pp. 26-28, 2009. (pdf)
  3. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs," ACM/IEEE International Workshop on System Level Interconnect Prediction, 2009. (pdf)
  4. Dae Hyun Kim and Sung Kyu Lim, "Through-Silicon-Via-aware Delay and Power Prediction Model for Buffered Interconnects in 3D ICs," ACM/IEEE International Workshop on System Level Interconnect Prediction, 2010. (pdf)
Low Power Design Methods for 3D ICs
  1. Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, "Fine-Grained 3D IC Partitioning Study with A Multi-core Processor," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 5, No. 10, pp. 1393-1491, 2015. (pdf)
  2. Taigon Song, Shreepad Panth, Yoo-Jin Chae, and Sung Kyu Lim, "More Power Reduction with 3-Tier Logic-on-Logic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 35, No. 12, pp. 2056 - 2067, 2016. (pdf)
  3. Moongon Jung, Taigon Song, Yarui Peng, and Sung Kyu Lim, "Design Methodologies for Low Power 3D ICs with Advanced Tier Partitioning," IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 7, pp. 2109-2117, 2017. (pdf)
  4. Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, and Sung Kyu Lim, "How to Reduce Power in 3D IC Designs: A Case Study with OpenSPARC T2 Core," IEEE Custom Integrated Circuits Conference, 2013. (pdf)
  5. Young-Joon Lee and Sung Kyu Lim, "On GPU Bus Power Reduction with 3D IC Technologies," Design, Automation and Test in Europe, 2014. (pdf)
  6. Moongon Jung, Taigon Song, Yang Wan, Yarui Peng, and Sung Kyu Lim, "On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective," ACM Design Automation Conference, 2014. (pdf)
  7. Taigon Song, Moongon Jung, Yang Wan, Yarui Peng, and Sung Kyu Lim, "3D IC Power Benefit Study Under Practical Design Considerations", IEEE International Interconnect Technology Conference, 2015. (pdf)
  8. Taigon Song, Shreepad Panth, Yoo-Jin Chae, and Sung Kyu Lim, "Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection," IEEE International Conference on Computer-Aided Design, 2015. (pdf)
Mechanical Stress Issues in 3D ICs
  1. Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 8, pp. 1194-1207, 2012. (pdf)
  2. Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, and Sung Kyu Lim, "Impact of Mechanical Stress on the Full Chip Timing for TSV-based 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 6, pp. 905-917, 2013. (pdf)
  3. Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Mechanical Stress Impact on 3D IC Reliability and Mobility Variations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1694-1707, 2013. (pdf)
  4. Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," Communications of the ACM, Vol. 57, No. 1, pp. 107-115, 2014. Research Highlight (invited) (pdf)
  5. Can Rao, Tongqing Wang, Yarui Peng, Jie Cheng, Yuhong Liu, Sung Kyu Lim, and Xinchun Lu, "Residual Stress and Pop-Out Simulation for TSVs and Contacts in Via-Middle Processing," IEEE Transactions on Semiconductor Manufacturing, Vol. 30, No. 2, pp. 143-154, 2017. (pdf)
  6. Tianchen Wang, Sandeep Samal, Sung Kyu Lim, and Yiyu Shi, "Entropy Production Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications, " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 1, pp. 84-95, 2019. (pdf)
  7. Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, and David Z. Pan, "TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization," ACM Design Automation Conference, 2010. (pdf)
  8. Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, and Sung Kyu Lim, "Stress-Driven 3D-IC Placement with TSV Keep-Out Zone and Regularity Study," IEEE International Conference on Computer-Aided Design, 2010. (pdf)
  9. Joydeep Mitra, Moongon Jung, Suk-Kyu Ryu, Rui Huang, Sung Kyu Lim, and David Z. Pan, "A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs," IEEE Electronic Components and Technology Conference, 2011. (pdf)
  10. Moongon Jung, Joydeep Mitra, David Z. Pan, and Sung Kyu Lim, "TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC," ACM Design Automation Conference, 2011. Nominated for Best Paper Award. (pdf)
  11. Moongon Jung, Xi Liu, Suresh Sitaraman, David Z. Pan and Sung Kyu Lim, "Full-Chip Through-Silicon-Via Interfacial Crack Analysis and Optimization for 3D IC," IEEE International Conference on Computer-Aided Design, 2011. (pdf)
  12. David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, and Jae-seok Yang, "Design for Manufacturability and Reliability for TSV-based 3D ICs," IEEE/ACM Asia South Pacific Design Automation Conference, 2012. Invited Paper. (pdf)
  13. Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Chip/Package Co-Analysis of Thermo-Mechanical Stress and Reliability in TSV-based 3D ICs," ACM Design Automation Conference, 2012. Nominated for Best Paper Award. (pdf)
  14. Chun Zhang, Moongon Jung, Sung Kyu Lim and Yiyu Shi, "Novel Crack Sensor Design for TSV-based 3D Integrated Circuits: Design and Deployment Perspectives," IEEE International Conference on Computer-Aided Design, 2013. (pdf)
  15. Moongon Jung, David Z. Pan, and Sung Kyu Lim, "Impact of Material Property Variations on Full-Chip Reliability and Performance in TSV-based 3D ICs," IEEE International Interconnect Technology Conference, 2014. (pdf)
  16. Tianchen Wang, Sandeep K. Samal, Sung Kyu Lim, and Yiyu Shi, "A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis," IEEE International Conference on Computer-Aided Design, 2015.
  17. Can Rao, Yarui Peng, Tongqing Wang, Sung Kyu Lim, and Xinchun Lu, "Investigation of Post-Annealing Stress and Pop-Out in TSV Front-side CMP," IEEE International Conference on Planarization/CMP Technology, 2016. Best Paper Award.
Monolithic, Hybrid Bonding, and Micro-bumping 3D IC Design and EDA
  1. Young-Joon Lee and Sung Kyu Lim, "Ultra High Density Logic Designs using Monolithic 3D Integration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 12, pp. 1892-1905, 2013. (pdf)
  2. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 4, pp. 540-553, 2015. (pdf)
  3. Sandeep Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du, and Sung Kyu Lim, "Adaptive Regression-based Thermal Modeling and Optimization for Monolithic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 35, No. 10, pp. 1707-1720, 2016. (pdf)
  4. Yun Seop Yu, Shreepad Panth, and Sung Kyu Lim, "Electrical Coupling of Monolithic 3D Inverters," IEEE Transactions on Electron Devices, Vol. 63, No. 8, pp. 3346-3349, 2016. (pdf)
  5. Sandeep Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, "Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 6, pp. 992-1003, 2017. (pdf)
  6. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Tier Degradation of Monolithic 3D ICs: A Power Performance Study at Different Technology Nodes," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 8, pp. 1265-1273., 2017. (pdf)
  7. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Shrunk-2D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 10, pp. 1716-1724, 2017. (pdf)
  8. Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Impact and Design Guideline of Monolithic 3D IC at the 7nm Technology Node," IEEE Transactions on Very Large Scale Integration Systems, Vol. 25, No. 7, pp. 2118-2129, 2017. (pdf)
  9. Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Parasitic Extraction for Heterogenous Face-to-Face Bonded 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 7, No. 6, pp. 912-924, 2017. (pdf)
  10. Yarui Peng, Dusan Petranovic, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, "Inter-die Coupling Extraction and Physical Design Optimization for Face-to-Face 3D ICs," IEEE Transactions on Nanotechnology, Vol. 17, No. 4, pp. 634-644, 2018. (pdf)
  11. Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-Sun Seo, and Sung-Kyu Lim, "Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition," ACM Journal on Emerging Technologies in Computing Systems, Vol. 14, No. 4, Article 42, 2018. (pdf)
  12. Tae Jun Ahn, Rakesh Perumal, Sung Kyu Lim, and Yun Seop Yu, "Parameter Extraction and Power/Performance Analysis of Monolithic 3D Inverter (M3INV)," IEEE Transactions on Electron Devices. Vol. 66, No. 2, pp. 1006-1011, 2019. (pdf)
  13. Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "System-Level Power Delivery Network Analysis and Optimization for Monolithic 3D ICs," IEEE Transactions on Very Large Scale Integration Systems. Vol. 27, No. 4, pp. 888-898, 2019. (pdf)
  14. Sai Pentapati, Lingjun Zhu, Lennart Bamberg, Da Eun Shim, Alberto Garcia-Ortiz, and Sung Kyu Lim, "A Logic-on-Memory Processor-System Design with Monolithic 3D Technology," IEEE Micro. Vol. 39, No. 6, pp. 38-45, 2019. (pdf)
  15. Tae Jun Ahn, Bum Ho Choi, Sung Kyu Lim, and Yun Seop Yu1, "Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory," Micromachines, Vol. 10, No. 637, 2019. (pdf)
  16. Bon Woong Ku, Kyungwook Chang, and Sung Kyu Lim, "Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-level 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 39, No. 6, pp. 1151-1164, 2020. Donald O. Pederson Best Paper Award. (pdf)
  17. Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, and Krishnendu Chakrabarty, "Advances in Design and Test of Monolithic 3D ICs," IEEE Design & Test. Vol. 37, No. 4, pp. 92-100, 2020. (pdf)
  18. Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto Garcia-Ortiz, and Sung Kyu Lim, "Heterogeneous 3D Integration for a RISC-V System with STT-MRAM," IEEE Computer Architecture Letters. Vol. 19, No. 1, pp. 51-54, 2020. (pdf)
  19. Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, and Sung Kyu Lim, "Heterogeneous Mixed-Signal Monolithic 3D In-Memory Computing Using Resistive RAM," IEEE Transactions on Very Large Scale Integration Systems. Vol. 29, No. 2, pp. 386-396, 2021. (pdf)
  20. Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Design-aware Partitioning-based 3D IC Design Flow with 2D commercial Tools," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 41, No. 3, pp. 410-423, 2021. (pdf)
  21. Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, and Sung Kyu Lim, "Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements," ACM Transactions on Design Automation of Electronic Systems. Vol. 26, No. 5, pp. 1-25, 2021. (pdf)
  22. Lingjun Zhu, Lennart Bamberg, Sai Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto Garcia-Ortiz, and Sung Kyu Lim, "High-Performance Logic-on-Memory Monolithic 3D IC Designs for Arm Cortex-A Processors," IEEE Transactions on Very Large Scale Integration Systems. Vol. 29, No. 6, pp. 1152-1163, 2021. (pdf)
  23. Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshawr Kannan, Krishnendu Chakrabarty and Sung Kyu Lim, "Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs", ACM Journal on Emerging Technologies in Computing Systems. Vol. 18, No. 1, pp. 1-37, 2021. (pdf)
  24. Edward Lee, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim and Saibal Mukhopadhyay, "A ReRAM Memory Compiler for Monolithic-3D Integrated Circuits in a Carbon Nanotube Process," ACM Journal on Emerging Technologies in Computing Systems. Vol. 18, No. 1, pp. 1-20, 2021. (pdf)
  25. Lingjun Zhu, Arjun Chaudhuri, Sanmitra Banerjee, Gauthaman Murali, Pruek Vanna-iampikul, Krishnendu Chakrabarty, and Sung Kyu Lim, "Design Automation and Test Solutions for Monolithic 3D ICs," ACM Journal on Emerging Technologies in Computing Systems. Vol. 18, No. 1, pp. 1-49, 2021. Keynote Paper. (pdf)
  26. Sai Pentapati, Bon Woong Ku, and Sung Kyu Lim, "Machine Learning Integrated Pseudo-3D Flow for Monolithic 3D ICs," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits. Vol. 7, No. 1, pp. 35-42, 2021. (pdf)
  27. Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, and Krishnendu Chakrabarty, "Power Supply Noise-aware At-speed Delay Fault Testing of Monolithic 3D ICs," IEEE Transactions on Very Large Scale Integration Systems. Vol. 29, No. 11, pp. 1875-1888, 2021. (pdf)
  28. Jinwoo Kim, Bon Woong Ku, Junsik Yoon, and Sung Kyu Lim, "An Effective Block Pin Assignment Approach for Block-level Monolithic 3D ICs," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits. Vol. 7, No. 1, pp. 26-34, 2021. (pdf)
  29. Daehyun Kim, Edward Lee, Jamin Seo, Jinwoo Kim, Sung Kyu Lim and Saibal Mukhopadhyay, "An SRAM Compiler for Monolithic-3D Integrated Circuit with Carbon Nanotube Transistors," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits. Vol. 7, No. 2, pp. 106-114, 2021. (pdf)
  30. Yi-Chen Lu, Sai Pentapati, Lingjun Zhu, Gauthaman Murali, Kambiz Samadi, and Sung Kyu Lim, "A Machine Learning Powered Tier Partitioning Methodology for Monolithic 3D ICs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 41, No. 11, pp. 4575-4586, 2022. (pdf)
  31. Tae Jun Ahn, Sung Kyu Lim, and Yun Seop Yu, "Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation," Applied Sciences, Vol. 11, No. 24. 2021. (https://doi.org/10.3390/app112412151)
  32. Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad Bakir, Suman Datta and Shimeng Yu, "A Compute-in-Memory Hardware Accelerator Design with Back-end-of-line (BEOL) Transistor based Reconfigurable Interconnect," IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Vol. 12, No. 2, pp. 445-457, 2022. (pdf)
  33. Sai Pentapati and Sung Kyu Lim, "Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs," IEEE Transactions on Very Large Scale Integration Systems. Vol. 30, No. 9, pp. 1355-1367, 2022. (pdf)
  34. Lingjun Zhu and Sung Kyu Lim, "Power Delivery Solutions and PPA impacts in Micro-Bump and Hybrid Bonding 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology. Vol. 12, No. 12, pp. 1969-1982, 2022. (pdf)
  35. Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Yun Heo, Jae-seung Choi, and Sung Kyu Lim, "Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 42, No. 7, pp. 2331-2335, 2023. (pdf)
  36. Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Sung Kyu Lim, and Krishnendu Chakrabarty, "Built-in self-test of high-density and realistic ILV layouts in monolithic 3D ICs," IEEE Transactions on Very Large Scale Integration Systems. Vol. 31, No. 3, pp. 296-309, 2022. (pdf)
  37. Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Gioele Mirabelli, Manu Perumkunnil, and Sung Kyu Lim, "Power, Performance, Area, and Cost Analysis of Face-to-Face Bonded 3D ICs," IEEE Transactions on Components, Packaging, and Manufacturing Technology. (pdf)
  38. Shao-Chun Hung, Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, and Krishnendu Chakrabarty, "Transferable Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (pdf)
  39. Gauthaman Murali, Aditya Iyer, Lingjun Zhu, Jianming Tong, Francisco Munoz Martinez, Srivatsa Rangachar Srinivasa, Tanay Karnik, Tushar Krishna, and Sung Kyu Lim, "On Continuing DNN Accelerator Architecture Scaling Using Tightly-coupled Compute-on-Memory 3D ICs," IEEE Transactions on Very Large Scale Integration Systems. (pdf)
  40. Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim, "A PPA Study for Heterogeneous 3D IC Options: Monolithic, Hybrid Bonding, and Micro-bumping," IEEE Transactions on Very Large Scale Integration Systems. Accepted for publication.
  41. Sai Pentapati, Kyungwook Chang, and Sung Kyu Lim, "Pin-3D: An Effective Physical Design Methodology for MultiDie Co-Optimization in Monolithic 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Accepted for publication.
  42. Sai Pentapati and Sung Kyu, "Heterogeneous Monolithic 3D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs," IEEE Transactions on Very Large Scale Integration Systems. Accepted for publication.
  43. Nesara Bethur, Anthony Agnesina, Moritz Brunion, Alberto Garcia-Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus Cavalcante, Samuel Riedel, Luca Benini, and Sung Kyu Lim, "Hier-3D: A Methodology for Physical Hierarchy Exploration of 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Accepted for publication.
  44. Yen-Hsiang Huang, Sai Pentapati, Anthony Agnesina, Moritz Brunion, and Sung Kyu Lim, "On Legalization of Die Bonding Bumps and Pads for 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Accepted for publication.
  45. Chang Liu and Sung Kyu Lim, "A Design Tradeoff Study with Monolithic 3D Integration," IEEE International Symposium on Quality Electronic Design, 2012. (pdf)
  46. Chang Liu and Sung Kyu Lim, "Ultra-High Density 3D SRAM Cell Designs for Monolithic 3D Integration," IEEE International Interconnect Technology Conference, 2012. (pdf)
  47. Young-Joon Lee, Patrick Morrow, and Sung Kyu Lim, "Ultra High Density Logic Designs Using Transistor-Level Monolithic 3D Integration," IEEE International Conference on Computer-Aided Design, 2012. (pdf)
  48. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "High-Density Integration of Functional Modules Using Monolithic 3D-IC Technology," IEEE/ACM Asia South Pacific Design Automation Conference, 2013. (pdf)
  49. Young-Joon Lee, Daniel Limbrick, and Sung Kyu Lim, "Power Benefit Study for Ultra-High Density Transistor-Level Monolithic 3D ICs," ACM Design Automation Conference, 2013. (pdf)
  50. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs," ACM International Symposium on Physical Design, 2014. Nominated for Best Paper Award. (pdf)
  51. Sandeep Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du, and Sung Kyu Lim, "Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs," ACM Design Automation Conference, 2014. (pdf)
  52. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations," ACM Design Automation Conference, 2014. Nominated for Best Paper Award. (pdf)
  53. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs," IEEE International Symposium on Low Power Electronics and Design, 2014. (pdf)
  54. Sandeep Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, "Full Chip Impact Study of Power Delivery Network Designs in Monolithic 3D ICs," IEEE International Conference on Computer-Aided Design, 2014. (pdf)
  55. Shreepad Panth, Sandeep Samal, Yun Seop Yu, and Sung Kyu Lim, "Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2014. Invited Paper. (pdf)
  56. Yarui Peng, Moongon Jung, Taigon Song, Yang Wan, and Sung Kyu Lim, "Thermal Impact Study of Block Folding and Face-to-Face Bonding in 3D IC", IEEE International Interconnect Technology Conference, 2015. (pdf)
  57. Taigon Song, Arthur Nieuwoudt, and Sung Kyu Lim, "Coupling Capacitance in Face-to-Face (F2F) Bonded 3D ICs: Trends and Implications," IEEE Electronic Components and Technology Conference, 2015. (pdf)
  58. Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs," IEEE International Conference on Computer-Aided Design, 2015. (pdf)
  59. Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Tier-Partitioning for Power Delivery vs Cooling Tradeoff in 3D VLSI for Mobile Applications," ACM Design Automation Conference, 2015. (pdf)
  60. Neela Lohith Penmetsa, Christos Sotiriou, and Sung Kyu Lim, "Low Power Monolithic 3D IC Design of Asynchronous AES Core," IEEE International Symposium on Asynchronous Circuits and Systems, 2015. (pdf)
  61. Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Power Benefit Study of Monolithic 3D IC at the 7nm Technology Node", IEEE International Symposium on Low Power Electronics and Design, 2015. (pdf)
  62. Deepak Nayak, Srinivasa Banna, Sandeep Samal, and Sung Kyu Lim, "Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2015. (pdf)
  63. Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Monolithic 3D IC Design: Power, Performance, and Area Impact at 7nm," IEEE International Symposium on Quality Electronic Design, 2016. (pdf)
  64. Sandeep Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, "Impact of Transistor Technology on Power Saving in Monolithic 3D ICs," International Symposium on VLSI Technology, Systems and Applications, 2016. (pdf)
  65. Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Match-making for Monolithic 3D IC: Finding the Right Technology Node," ACM Design Automation Conference, 2016. (pdf)
  66. Yosef Borga, Daniel Limbrick, and Sung Kyu Lim, "Physical Design Factors that contribute to Routing Congestion in Monolithic 3D Integrated Circuits," ACM International Workshop on Logic and Synthesis, 2016.
  67. Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, and Sung Kyu Lim, "Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design, 2016. (pdf)
  68. Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study," ACM/IEEE International Symposium on Low Power Electronics and Design, 2016. (pdf)
  69. Sandeep Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, "How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions," ACM/IEEE International Symposium on Low Power Electronics and Design, 2016. (pdf)
  70. Sandeep Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, "Monolithic 3D IC vs TSV-based 3D IC in 14nm FinFET Technology," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2016. (pdf)
  71. Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan and Sung Kyu Lim, "How Much Cost Reduction Justifies the Adoption of Monolithic 3D ICs at 7nm Node?" IEEE International Conference on Computer-Aided Design, 2016. (pdf)
  72. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna and Sung Kyu Lim, "Tier Partitioning Strategy to Mitigate BEOL Degradation and Cost Issues in Monolithic 3D ICs," IEEE International Conference on Computer-Aided Design, 2016. (pdf)
  73. Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric and Sung Kyu Lim, "Cascade2D: A Design-Aware Partitioning Approach to Monolithic 3D IC with 2D Commercial Tools," IEEE International Conference on Computer-Aided Design, 2016. (pdf)
  74. Jiajun Shi, Deepak Nayak, Srinivasa Banna, Robert Fox, Srikanth Samavedam, Sandeep Samal, and Sung Kyu Lim, "A 14nm Finfet Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC," IEEE International Electron Devices Meeting, 2016. (pdf)
  75. Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, and Sung Kyu Lim, "Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design, 2017. (pdf)
  76. Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, and Sung Kyu Lim, "Transistor-Level Monolithic 3D Standard Cell Layout Optimization for Full-Chip Static Power Integrity," ACM/IEEE International Symposium on Low Power Electronics and Design, 2017. (pdf)
  77. Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, and Sung Kyu Lim, "Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition," ACM/IEEE International Symposium on Low Power Electronics and Design, 2017. (pdf)
  78. Kyungwook Chang, Abhishek Koneru, Krishnendu Chakrabarty, and Sung Kyu Lim, "Design Automation and Testing of Monolithic 3D ICs: Opportunities, Challenges, and Solutions," IEEE International Conference on Computer-Aided Design, 2017. (pdf)
  79. Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, and Sung Kyu Lim, "Full-chip Monolithic 3D IC Design and Power Performance Analysis with ASAP7 Library," IEEE International Conference on Computer-Aided Design, 2017. (pdf)
  80. A. Mallik, A. Vandooren, L. Witters, A. Walke, J. Franco, Y. Sherazi, P. Weckx, D. Yakimets, M. Bardon, B. Parvais, P. Debacker, B. W. Ku, S. K. Lim, A. Mocuta, D. Mocuta, J. Ryckaert, N. Collaert, and P. Raghavan, "The Impact of Sequential-3D Integration on Semiconductor Scaling Roadmap," IEEE International Electron Devices Meeting, 2017. (pdf)
  81. Bon Woong Ku, Kyungwook Chang, and Sung Kyu Lim, "Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs," ACM International Symposium on Physical Design, 2018. Nominated for Best Paper Award. (pdf)
  82. Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim, Quan Chen, Xiaoyao Liang, and Li Jiang, "In-growth Test for Monolithic 3D SRAM," Design, Automation and Test in Europe, 2018. (pdf)
  83. Kyungwook Chang, Sai Pentapati, Da Eun Shim, and Sung Kyu Lim, "Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design, 2018. (pdf)
  84. Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Samal, Peng Li, and Sung Kyu Lim, "Design and Architectural Co-optimization of Monolithic 3D Liquid State Machine-based Neuromorphic Processor," ACM Design Automation Conference, 2018. (pdf)
  85. Bon Woong Ku, Yu Liu, Yingyezhe Jin, Peng Li, and Sung Kyu Lim, "Area-efficient Low-power Face-to-Face-bonded 3D Liquid State Machine Design in the Internet-of-Things Era," IEEE International Conference on Computer-Aided Design, 2018. (pdf)
  86. Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, and Sung Kyu Lim, "RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs," ACM Design Automation Conference, 2019. Invited Paper. (pdf)
  87. Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, and Sung Kyu Lim, "Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs," IEEE European Test Symposium, 2019. (pdf)
  88. Sai Pentapati and Sung Kyu Lim, "Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary," ACM Great Lakes Symposium on VLSI, 2019. Invited Paper. (pdf)
  89. Da Eun Shim, Sai Pentapati, Jeehyun Lee, Yun Seop Yu, and Sung Kyu Lim, "Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design, 2019. (pdf)
  90. Lennart Bamberg, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Alberto Garcia-Ortiz, and Sung Kyu Lim, "Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs," Design, Automation and Test in Europe, 2020. (pdf)
  91. Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, and Sung Kyu Lim, "Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs," ACM International Symposium on Physical Design, 2020. (pdf)
  92. Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, and Sung Kyu Lim, "Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs," ACM International Symposium on Physical Design, 2020. Invited Paper. (pdf)
  93. Jinwoo Kim, Heechun Park, Edward Lee, Daehyun Kim, Arjun Chaudhuriy, Sanmitra Banerjeey, Mark Nelsonz, Krishnendu Chakrabartyy, Saibal Mukhopadhyay, and Sung Kyu Lim, "RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory," Government Microcircuit Applications and Critical Technonogy (GOMACTech) Conference, 2020.
  94. Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, and Sung Kyu Lim, "Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs," ACM International Symposium on Physical Design, 2020. Invited Paper. (pdf)
  95. Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim, "TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs," ACM Design Automation Conference, 2020. Nominated for Best Paper Award. (pdf)
  96. Bon Woong Ku and Sung Kyu Lim, "Pin-in-the-Middle: An Efficient Block Pin Assignment Methodology for Block-level Monolithic 3D ICs," ACM/IEEE International Symposium on Low Power Electronics and Design, 2020. (pdf)
  97. Sai Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, and Sung Kyu Lim, "Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs," IEEE International Conference on Computer-Aided Design, 2020. (pdf)
  98. Jinwoo Kim, Gauthaman Murali, Pruek Vanna-iampikul, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, and Sung Kyu Lim, "RTL-to-GDS Design Tools for Monolithic 3D ICs," IEEE International Conference on Computer-Aided Design, 2020. Invited Paper. (pdf)
  99. Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, and Krishnendu Chakrabarty, "Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs," IEEE Asian Test Symposium, 2020. (pdf)
  100. Gauthaman Murali and Sung Kyu Lim, "Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies", Design, Automation and Test in Europe, 2021. (pdf)
  101. Sai Pentapati, Bon Woong Ku, and Sung Kyu Lim, "ML-based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization," ACM International Symposium on Physical Design, 2021. (pdf)
  102. Pruek Vanna-Iampikul, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim, "Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs," ACM International Symposium on Physical Design, 2021. Nominated for Best Paper Award. (pdf)
  103. Lingjun Zhu and Sung Kyu Lim, "Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies," ACM International Symposium on Physical Design, 2021. Invited Paper. (pdf)
  104. Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, and Tushar Krishna, "Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators", IEEE International Symposium on Quality Electronic Design, 2021. (pdf)
  105. Sai Pentapati and Sung Kyu Lim, "Heterogeneous Monolithic 3D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs", ACM Design Automation Conference, 2021. (pdf)
  106. Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, and Sung Kyu Lim, "Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Comparative Study for Emerging Heterogeneous 3D Integration Options", ACM Design Automation Conference, 2021. (pdf)
  107. Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Manu Perumkunnil and Sung Kyu Lim, "Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs", ACM/IEEE International Symposium on Low Power Electronics and Design, 2021. Nominated for Best Paper Award. (pdf)
  108. Lingjun Zhu, Saurabh Sinha, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline and Sung Kyu Lim, "Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture", ACM/IEEE International Symposium on Low Power Electronics and Design, 2021. (pdf)
  109. Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali, Marc Nelson, Sung Kyu Lim, and Krishnendu Chakrabarty, "ParaMitE: Mitigating parasitic CNFETs in the presence of unetched CNTs", IEEE International Conference on Computer-Aided Design, 2021. (pdf)
  110. Yandong Luo, Sourav Dutta, Ankit Kaul, Sung Kyu Lim, Muhannad Bakir, Suman Datta, and Shimeng Yu, "Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect", IEEE International Electron Devices Meeting, 2021. Invited Paper. (pdf)
  111. Matheus Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto Garcia-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, and Luca Benini, "MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration", Design, Automation and Test in Europe, 2022. (pdf)
  112. Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, and Sung Kyu Lim, "ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs", ACM International Symposium on Physical Design, 2022. (pdf)
  113. Sai Pentapati and Sung Kyu Lim, "Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs", ACM International Symposium on Physical Design, 2022. (pdf)
  114. Anthony Agnesina, Moritz Brunion, Alberto Garcia-Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus Cavalcante, Samuel Riedel, Luca Benini, and Sung Kyu Lim, "Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face Bonded 3D ICs", ACM/IEEE International Symposium on Low Power Electronics and Design, 2022. Best Paper Award. (pdf)
  115. Lingjun Zhu, Nesara Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, and Sung Kyu Lim, "3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs", ACM/IEEE International Symposium on Low Power Electronics and Design, 2022. (pdf)
  116. Tathagata Srimani, Robert Radway, Jinwoo Kim, Kartik Prabhu, Dennis Rich, Carlo Gilardi, Priyanka Raina, Max Shulaker, Sung Kyu Lim, and Subhasish Mitra, "Ultra-Dense 3D Physical Design Enables New Architectural Design Points with Large Benefits", Design, Automation and Test in Europe, 2023. (pdf)
  117. Sai Pentapati, Yen-Hsiang Huang, and Sung Kyu Lim, "On Legalization of Die Bonding Bumps and Pads for 3D ICs", ACM International Symposium on Physical Design, 2023. (pdf)
  118. Narasinga Rao Miniskar, Pruek Vanna-iampikul, Aaron Young, Sung Kyu Lim, Frank Liu, Jieun Yoo, Corrinne Mills, Nhan Tran, Farah Fahim, and Jeffrey S. Vetter, "A 3D Implementation of Convolutional Neural Network for Fast Inference", IEEE International Symposium on Circuits & Systems, 2023. (pdf)
  119. Lingjun Zhu and Sung Kyu Lim, "Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps", ACM Design Automation Conference, 2023. Invited Paper. (pdf)
  120. Gauthaman Murali, Aditya Iyer, Navneeth Ravichandran and Sung Kyu Lim, "3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators", IEEE/ACM International Conference On Computer Aided Design, 2023. (pdf)
  121. Hao-Hsiang Hsiao, Pruek Vanna-iampikul, Yi-Chen Lu, and Sung Kyu Lim, "ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization", ACM Design Automation Conference, 2024.
  122. Nesara Eranna Bethur, Pruek Vanna-iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto Garcia-Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, and Sung Kyu Lim, "GNN-assisted Back-side Clock Routing Methodology for Advance Technologies", ACM Design Automation Conference, 2024.
  123. Lingjun Zhu, Jiawei Hu, Gauthaman Murali, and Sung Kyu Lim, "Hetero-3D: PPA and Power Delivery Benefits of Heterogeneous 3D ICs with a Customized Physical Design Flow", ACM/IEEE International Symposium on Low Power Electronics and Design, 2024.
  124. Aditya Iyer, Daehyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line Folding", IEEE/ACM International Conference on Computer-Aided Design, 2024.
  125. Boxun Xu, Junyoung Hwang, Pruek Vanna-iampikul, Sung Kyu Lim, and Peng Li, "Spiking Transformer Hardware Accelerators in 3D Integration", IEEE/ACM International Conference on Computer-Aided Design, 2024.
  126. Pruek Vanna-iampikul, Junsik Yoon, Chaeryung Park, Gary Yeap, and Sung Kyu Lim, "Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICs", ACM International Symposium on Physical Design, 2025.
Other Topics in 3D ICs
  1. Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Samal, Sung Kyu Lim, and Ankur Srivastava, "TSV-based 3D ICs: Design Methods and Tools," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 10, pp. 1593-1619, 2017. Keynote Paper. (pdf)
  2. Dae Hyun Kim, Yen-Kuan Wu, Rasit Onur Topaloglu, and Sung Kyu Lim, "Enabling 3D Integration Through Optimal Topography," IEEE International Workshop on Design for Manufacturability and Yield, 2010. (pdf)
  3. Mohit Pathak and Sung Kyu Lim, "Reliability and Performance-aware 3D SRAM Design," IEEE International Midwest Symposium on Circuits and Systems, 2011. (pdf)
  4. Seung-Ho Ok, Kyeong-ryeol Bae, Sung Kyu Lim and Byungin Moon, "Design and Analysis of 3D IC-Based Low Power Stereo Matching Processors," IEEE International Symposium on Low Power Electronics and Design, 2013. (pdf)
  5. Woongrae Kim, Dae-Hyun Kim, Hee Il Hong, Linda Milor, and Sung Kyu Lim, "Impact of Die Partitioning on Reliability and Yield of 3D DRAM," IEEE International Interconnect Technology Conference, 2014. (pdf)
  6. Dae Hyun Kim and Sung Kyu Lim, "Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities," IEEE Design and Test, Vol. 32, No. 4, pp. 8-22, 2015. (pdf)
  7. Hourieh Attarzadeh, Sung Kyu Lim, and Trond Ytterdal, "Stacking Integration Methodologies in 3D IC for 3D Ultrasound Image Processing Application: A Stochastic Flash ADC Design Case Study," IEEE International Symposium on Circuits and Systems, 2015. (pdf)
Parasitic Extractions for 3D ICs
  1. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 2, pp. 168-180, 2011. (pdf)
  2. Yarui Peng, Taigon Song, Dusan Petranovic, and Sung Kyu Lim, "Silicon Effect-aware Full-chip Extraction and Mitigation of TSV-to-TSV Coupling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 12, pp. 1900-1913, 2014. (pdf)
  3. Yarui Peng, Dusan Petranovik, and Sung Kyu Lim, "Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-wire Coupling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 12, pp. 1964-1976, 2015. (pdf)
  4. Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, "Full-Chip Signal Integrity Analysis and Optimization of 3D ICs," IEEE Transactions on Very Large Scale Integration Systems, Vol. 24, No. 5, pp. 1636-1648, 2016. (pdf)
  5. Chang Liu and Sung Kyu Lim, "A Study of Signal Integrity Issues in Through-Silicon-Via-based 3D ICs," IEEE International Interconnect Technology Conference, 2010. (pdf)
  6. Taigon Song, Chang Liu, Dae Hyun Kim, Jonghyun Cho, Joohee Kim, Jun So Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon and Sung Kyu Lim, "Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs," IEEE International Symposium on Quality Electronic Design, 2011. (pdf)
  7. Chang Liu, Taigon Song and Sung Kyu Lim, "Signal Integrity Analysis and Optimization for 3D ICs," IEEE International Symposium on Quality Electronic Design, 2011. (pdf)
  8. Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, and Sung Kyu Lim, "Full-Chip TSV-to-TSV Coupling Analysis and Optimization in 3D IC," ACM Design Automation Conference, 2011. (pdf)
  9. Taigon Song, Chang Liu, Yarui Peng, and Sung Kyu Lim, "Full-Chip Multiple TSV-to-TSV Coupling Extraction and Optimization in 3D ICs," ACM Design Automation Conference 2013. (pdf)
  10. Yarui Peng, Taigon Song, Dusan Petranovic and Sung Kyu Lim, "On Accurate Full-Chip Extraction and Optimization of TSV-to-TSV Coupling Elements in 3D ICs," IEEE International Conference on Computer-Aided Design, 2013. (pdf)
  11. Yarui Peng, Dusan Petranovik, and Sung Kyu Lim, "Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling," ACM Design Automation Conference, 2014. (pdf)
Power Delivery Issues in 3D ICs
  1. Michael B. Healy and Sung Kyu Lim, "Distributed TSV Topology for 3D Power-Supply Networks," IEEE Transactions on Very Large Scale Integration Systems, Vol. 20, No. 11, pp. 2066-2079, 2012. (pdf)
  2. Micheal Healy and Sung Kyu Lim, "Power Delivery System Architecture for Many-Tier 3D Systems," IEEE Electronic Components and Technology Conference, 2010. (pdf)
  3. Moongon Jung and Sung Kyu Lim, "A study of IR-drop noise issues in 3D ICs with Through-Silicon-Vias," IEEE International 3D System Integration Conference, 2010. (pdf)
  4. Michael Healy and Sung Kyu Lim, "Power-Supply-Network Design in 3D Integrated Systems," IEEE International Symposium on Quality Electronic Design, 2011. (pdf)
  5. Michael Healy and Sung Kyu Lim, "A Novel TSV Topology for Many-Tier 3D Power-Delivery Networks," Design, Automation and Test in Europe, 2011. (pdf)
  6. Moongon Jung, Shreepad Panth, and Sung Kyu Lim, "A Study of TSV Variation Impact on Power Supply Noise," IEEE International Interconnect Technology Conference, 2011. (pdf)
  7. Yarui Peng, Bon Woong Ku, Younsik Park, Kwang-Il Park, Seong-Jin Jang, Joo Sun Choi, and Sung Kyu Lim, "Design, Packaging, and Architectural Policy Co-Optimization for DC Power Integrity in 3D DRAM," ACM Design Automation Conference, 2015. (pdf)
Routing for 3D ICs
  1. Jacob Minz and Sung Kyu Lim, "Block-level 3D Global Routing With an Application to 3D Packaging," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 2248-2257, 2006. (pdf)
  2. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 4, pp. 805-812, 2007. (pdf)
  3. Mohit Pathak and Sung Kyu Lim, "Performance and Thermal-aware Steiner Routing for 3D Stacked ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 9, pp. 1373-1386, 2009. (pdf)
  4. Jacob Minz and Sung Kyu Lim, "Layer Assignment for System on Packages," ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 31-37, 2004. (pdf)
  5. Jacob Minz, Mohit Pathak, and Sung Kyu Lim, "Net and Pin Distribution for 3D Package Global Routing," Design, Automation and Test in Europe, pp. 1410-1411, 2004. (pdf)
  6. Jacob Minz and Sung Kyu Lim, "A Global Router for System-on-Package Targeting Layer and Crosstalk Minimization," IEEE Electrical Performance of Electronic Packaging, pp. 99-102, 2004. (pdf)
  7. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," Design, Automation and Test in Europe, pp. 337-338, 2006. (pdf)
  8. Mohit Pathak and Sung Kyu Lim, "Thermal-aware Steiner Routing for 3D Stacked ICs," IEEE International Conference on Computer-Aided Design, pp. 205-211, 2007. (pdf)
Sub/Near-Threshold 3D IC Design
  1. Jeremy Tolbert, Xin Zhao, Sung Kyu Lim, and Saibal Mukhopadhyay, "Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 9, pp. 1349-1358, 2011. (pdf)
  2. Xin Zhao, Jeremy Tolbert, Saibal Mukhopadhyay, and Sung Kyu Lim, "Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 8, pp. 1222-1234, 2012. (pdf)
  3. Sandeep Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, "Ultralow Power Circuit Design With Subthreshold/Near-Threshold 3-D IC Technologies," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 5, No. 7, pp. 980 - 990, 2015. (pdf)
  4. Sandeep Samal, Guoqing Chen, and Sung Kyu Lim, "Improving Performance Under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs," ACM Journal on Emerging Technologies in Computing Systems, Vol. 13, No. 4, Article 59, 2017. (pdf)
  5. Jeremy Tolbert, Xin Zhao, Saibal Mukhopadhyay, and Sung Kyu Lim, "Slew-Aware Clock Tree Design For Reliable Subthreshold Circuits," IEEE International Symposium on Low Power Electronics and Design, 2009. (pdf)
  6. Xin Zhao, Jeremy Tolbert, Chang Liu, Saibal Mukhopadhyay, and Sung Kyu Lim, "Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits," IEEE International Symposium on Low Power Electronics and Design, 2011. (pdf)
  7. Sandeep Samal, Yarui Peng, Yang Zhang and Sung Kyu Lim, "Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs," IEEE International Symposium on Low Power Electronics and Design, , pp. 21-26, 2013. (pdf)
  8. Sandeep Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim and Sung Kyu Lim, "Ultra Low Power 2-tier 3D Stacked Sub-threshold H.264 Intra Frame Encoder," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2013. (pdf)
  9. Sandeep Samal, Yang Li, Guoqing Chen, and Sung Kyu Lim, "Improving Performance in Near-Threshold Circuits Using 3D IC Technology," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, 2015. (pdf)