GTCAD Project List

1. GP-3D: Georgia Tech Placer for True 3D IC Placement (Samsung, 2019-26)
2. 3D Memory/Logic Stacking Architecture Exploration (IMEC, 2020-24)
3. Enabling Design Space Exploration of Monolithic-3D Logic and Memory Fabrics (SRC, 2023-25)
4. Design Automation for Monolithic 3D and Heterogeneous Interposer Integration (SRC JUMP 2.0, 2023-27)
5. A Multi-tier Fine-Grained 3D Architecture for Efficient Inference and Training of Memory-Intensive AI Workloads (TSMC, 2023-25)
6. System-level Evaluation of Monolithic 3D ICs Based on 2D Materials Transistors and Remote Epitaxy (Samsung, 2023-24)
7. Routing Design Guided Development of 3D Scaling BEOL Interconnect Technology (KEIT, 2023-27)
8. ML-based Generation of Fine-grained TSV Models for Power Integrity Analysis (NSF, 2024-26)
9. AI-based Physical Design Automation for 2D and 3D ICs (Samsung, 2024-27)
10. Physical Design Closure with Machine Learning (Synopsys, 2021-25)

1. Interconnect-centric Physical Design Methodology (GA Yamacraw, 2001-3)
2. Noise Immune On/Off Chip 3-D Routing for High Speed System-On-Package Substrate (NSF, 2002-4)
3. Chip/Package Co-design of Physical Layout for Fast and Reliable System-On-Packages (ACM DAC, 2003-4)
4. Placement and Routing for Polymorphic Computing Architecture (DARPA, 2003-4)
5. NER: Automatic Placedment Algorithms For Quantum-Dot Cellular Automata (NSF, 2004-5)
6. Bringing Low Power Reconfigurable Analog Signal Processing To Embedded Systems (NSF, 2004-7)
7. Mixed Signal Design Tool for System-On-Package (NSF/PRC, 2007-9)
8. High-Performance 3D Microarchitecture Design (SRC/GSRC, 2005-6)
9. High-Performance 3D Microarchitecture Design (SRC/C2S2, 2006-9)
10. CAREER: Physical Design Automation for Fast and Reliable 3D Circuits (NSF, 2006-11)
11. Design for Manufacturing Issues with Through-Silicon-Via (Intel, 2009-11)
12. A Digital Infomedia System - Immersive Technologies on a Hybrid GPU-CPU Platform (KIAT, 2009-12)
13. Co-Optimization and Limit Study of Thermal, Power, Clock, and Signal Distribution Networks in 3D ICs (SRC/IFC, 2007-12)
14. Reliability and Standardization Study for TSV-based Wide I/O DRAM Structures in 3D-IC Integration (SRC, 2011-12)
15. High Density 3D SRAM and Logic Designs with Monolithic 3D Integration (SRC/ICSS, 2011-12)
16. 3D Integration of Sub-Threshold Multi-core Co-processor for Ultra Lower Power Computing (NSF, 2009-13)
17. Design-for-Testing for TSV-based 3D DRAM (Samsung, 2012-14)
18. 3D IC Design for Ultra Low Power Wireless Sensor Network (CISS, 2012-14)
19. Design, Fabrication, and Testing of 3D-MAPS: A Massively Parallel Processor with 3D Stacked Memory (US DOD, 2009-14)
20. Design of 3D Integrated Heterogeneous Systems (SRC/ICSS, 2011-15)
21. Design for Manufacturability of 3D ICs with Through Silicon Vias (NSF, 2010-15)
22. Low Power Computing with Multi-core 3D Processors (Intel, 2012-15)
23. Low Power and Reliable Designs for Monolithic 3D ICs (Qualcomm, 2012-15)
24. CAD Tool and Methodology for Reliable 3D-IC Integration (SRC/CADTS, 2012-15)
25. Architecture-aware Power Distribution Network Design for Wide-I/O 3D DRAM (Samsung, 2013-15)
26. Power Delivery Network Design and CAD for Monolithic 3D ICs (ARM, 2016)
27. Parasitic Extraction for TSV-based 3D ICs (Mentor Graphics, 2014-16)
28. Next-generation Neuromorphic Coprocessor Power Consumption in the Beyond Exascale Era (Oak Ridge National Lab, 2016-18)
29. Exploration of Intrinsic Monolithic 3D IC Design Limits and PPA Analysis (TSMC, 2017-19)
30. Bringing 3D Memory Cubes to Space: A Rapid Prototyping Study and Experimental Validation (NASA, 2016-19)
31. Thermal-aware Tier Partitioning and Extraction for Wafer-bonded 3D ICs (SRC, 2017-19)
32. Machine Learning to Predict Successful FPGA Compilation Strategy (NSF, 2018-19)
33. A Vertically-Integrated Design Flow for IP Reuse and Heterogeneous Integration (DARPA, 2017-21)
34. FLASHRAD: A 3D Rad Hard Memory Module For High Performance Space Computers (NASA, 2017-20)
35. Netlist-to-PPA Prediction Using Machine Learning (NSF, 2019-21)
36. Device/Circuit Co-design of Negative Capacitance Transistors (NSF, 2017-21)
37. Power Delivery Network Comparison Between Micro-bump and Hybrid Bonding 3D ICs (Samsung, 2021-22)
38. Glass Interposer Integration of Logic and Memory Chiplets: PPA Benefits Over Other Means (PRC/Facebook, 2021-22)
39. Physical Design Tools for Monolithic 3D ICs Targeting Logic Applications (SRC, 2020-23)
40. RTL-to-GDS Tools and Methodologies for Sequential Integration Monolithic 3D ICs (DARPA, 2018-23)
41. Domain-Specific 3D ReRAM-based Processing-in-Memory Accelerators for Streaming Time Series Applications (NSF, 2023-24)
42. Abisko: Deep Codesign of an Energy-Optimized, High Performance Neuromorhpic Accelerator (DOE, 2021-24)
43. Physical Design Parameter Optimization (PDPO) Using Reinforcement Learning (NSF, 2023-25)