People of the GTCAD Laboratory

FACULTY

Sung Kyu Lim
Motorola Solutions Foundation Professor
School of Electrical and Computer Engineering
Georgia Institute of Technology

CURRENT MEMBERS

PHD STUDENTS

  1. Yen-Hsiang (Robert) Huang (Fall 2022)
  2. Hao-Hsiang (Thomas) Hsiao (Fall 2022)
  3. Hang Yang (Spring 2023, co-advised with Prof. Callie Hao)
  4. Amaan Rahman (Fall 2023)
  5. Jiawei Hu (Fall 2023)
  6. Min Gyu Park (Fall 2023)
  7. Seungmin Woo (Fall 2023)
  8. Sungwoo Jung (Fall 2023)
  9. Zheng Yang (Fall 2023)
  10. Yuan-Hsiang (Peter) Lu (Fall 2024)
  11. Cheng-Yu (Mike) Tsai (Fall 2024)
  12. Juyeop Baek (Fall 2024)
  13. Karthic Palaniappan (Fall 2024)
PAST MEMBERS

PHD ALUMNI

  1. Mongkol Ekpanyapong (2005), "Microarchitecture-Aware Physical Planning for Deep Submicron Technology", Asian Institute of Technology, Thailand.
  2. Jacob Minz (2006), "Physical design automation for System-on-Packages and 3D-Integrated Circuits", Synopsys.
  3. Faik Baskaya (2009), "Physical Design Automation for Field-Programmable Analog Array (FPAA)", Bogazici University, Turkey.
  4. Michael Healy (2010), "Physical Design For Performance and Thermal and Power-Supply Reliability in Modern 2D And 3D Microarchitectures", IBM.
  5. Dae Hyun Kim (2012), "Through-Silicon-Via-Aware Prediction and Physical Design for Multi-Granularity 3D Integrated Circuits", Washington State University.
  6. Krit Athikulwongse (2012), "Placement for Fast and Reliable Through-Silicon-Via (TSV) Based 3D-IC Layouts", National Electronics and Computer Technology Center, Thailand.
  7. Xin Zhao (2012), "Reliable Clock and Power Delivery Network Design for Three-Dimensional Integrated Circuits", IBM.
  8. Young Joon Lee (2013), "CAD Methogologies for Low Power and Reliable 3D ICs", Google.
  9. Moongon Jung (2014), "Low Power and Reliable Design Methodologies for 3D ICs", Intel.
  10. Shreepad Panth (2015), "Physical Design Methodologies for Monolithic 3D ICs", Intel.
  11. Taigon Song (2015), "Chip/Package Co-design Methodologies for Reliable 3D ICs", Kyungpook National University.
  12. Yarui Peng (2016), "CAD Tools and Methodologies for Reliable 3D IC Design, Analysis, and Optimization", University of Arkansas.
  13. Sandeep Samal (2017), "Design Challenges and CAD Solutions for Low Power and Reliable Monolithic 3D ICs", Intel.
  14. Kyungwook Chang (2018), "Design and Tool Solutions for Energy-Efficient Reliable Monolithic 3D ICs", Sungkyunkwan (SKK) University.
  15. Bon Woong Ku (2018), "Physical Design Solutions For 3D ICs and their Neuromorphic Applications", Synopsys.
  16. Anthony Agnesina (2022), "Electronic Design Automation for High-Performance and Reliable 3D Memory Cubes and Processors", NVIDIA.
  17. Jinwoo Kim (2022), "Electronic Design Automation Solutions and Design Tradeoffs for Emerging Heterogeneous 2.5D and 3D ICs", Intel.
  18. Sai Pentapati (2022), "Electronic Design Automation Tools and Design Study for Heterogeneous Monolithic 3D Integrated Circuits", Intel.
  19. Yi-Chen Lu (2023), "Machine Learning in Physical Design for 2D and 3D Integrated Circuits", Apple
  20. Da Eun Shim (2023), "Exploration, Modeling and Optimization of Advanced Interconnects: Solutions to Node Scaling Challenges", (co-advised with Prof. Azad Naeemi), Intel
  21. Lingjun Zhu (2023), "Power Delivery and Thermal-Aware Electronic Design Automation Solutions for High-Performance 3D ICs", Apple
  22. Gauthaman Murali (2023), "Design Methodologies of 2.5D and 3D Near-memory and In-memory Compute ML Accelerators", Intel
  23. Pruek Vanna-iampikul (2024), "Design Algorithms and Methodologies for Heterogeneous 2.5D and 3D Integrated Circuits", Burapha University, Thailand.
MS ALUMNI (THESIS OPTION)
  1. Ramprasad Ravichandran (2005), "Automatic Placement for Quantum Cell Automata", Twitter
  2. Hemant Sane (2010), "Parasitic RLC Model for P/G Netwoek in 3D Chips Using Through-Silicon-Vias", Samsung
  3. Neela Lohith (2014), "Monolithic 3D Integration of Asynchronous Systems", Apple
  4. Mohit Pathak (2014), "Performance and Reliability-Aware Physical Design for 3D IC and Package", Cadence
  5. Rakesh Perumal (2018), "Power and Performance Optimization of Negative Capacitance Transistor Circuits", NVIDIA
  6. Nesara Bethur (2023), "A Methodology for Back-side Clock Delivery Network Design Compatible with Commercial EDA Flows", AMD
  7. Sandra Shaji (2023), "3nm Nanosheet FET vs. FinFET Comparison and Optimization with device/circuit co-design framework", Samsung
  8. Aditya Iyer (2024), "A Physical Design Framework for Ceating Fiie-grained Multi-tier SRAM Arrays", Intel

POST-DOC ALUMNI

  1. Dr. Daniel Limbrick (2012-13)
  2. Dr. Heechun Park (2018-20)

VISITING PHD STUDENTS

  1. Seung-Ho Ok, Kyungpook National University (2011-13)
  2. Hee Chun Park, Seoul National University (2013)
  3. Young Chan Kim, Seoul National University (2013)
  4. Young-Ho Gong, Korea University (2013)
  5. Hourieh Atarzadeh, Norwegian University of Science and Technology (2014)
  6. Tianchen Wang, Missouri University of Science and Technology (2014)
  7. Jaewon Jang, Yonsei University (2015)
  8. Ingeol Lee, Yonsei University (2015)
  9. Can Rao, Tsinghua University (2016)
  10. Hantao Huang, Nanyang Technological University (2017)
  11. Karim Rawy, Nanyang Technological University (2017)
  12. Lennart Bamberg, University of Bremen (2019)
  13. Zhen Zhuang, Chinese University of Hong Kong (2024)
  14. Junjong Lee, POSTECH (2024)

VISITING ENGINEERS

  1. Hee-il Hong, Samsung Electronics (2012-13)
  2. Debabrata Mohapatra, Intel Corporation (2013)
  3. Younsik Park, Samsung Electronics (2013-14)
  4. Chanmin Jo, Samsung Electronics (2021-22)
RESEARCH ASSOCIATES
  1. Prof. Junsik Yoon, POSTECH (2021-2022)
VISITING SCHOLARS
  1. Link
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